View MT9P031_6420390.PDF datasheet online --- IC-ON-LINE

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. MT9P031: 1/2.5-inch 5mp digital image sensor features pdf: 0548592346/source:9863314264 . MT9P031_ds - rev. f 5/11 en 1 ?2005 aptina imaging corporation all rights reserved. 1/2.5-inch 5mp cmos digital image sensor MT9P031 for the latest data sheet, refer to aptinas web site: www.aptina.com features ?high frame rate ? superior low-light performance ?low dark current ? global reset release, which starts the exposure of all rows simultaneously ? bulb exposure mode, for arbitrary exposure times ? snapshot mode to take frames on demand ? horizontal and vertical mirror image ? column and row skip modes to reduce image size without reducing field-of-view (fov) ? column and row binning modes to improve image quality when resizing ? simple two-wire serial interface ? programmable controls: gain , frame rate, frame size, exposure ? automatic black level calibration ? on-chip phase-locked loop (pll) applications ? high resolution network cameras ? wide fov cameras ? 720p?60 fps cameras ? dome cameras with electronic pan, tile, and zoom ? hybrid video cameras with high resolution stills ? detailed feature extraction for smart cameras ordering information table 1: available part numbers part number description MT9P031i12stc 48-pin ilcc 7 deg MT9P031i12std 48-pin ilcc es demo MT9P031i12sth 48-pin ilcc headboard table 2: key performance parameters the 5mp cmos image sensor features aptina?s break- through low-noise cmos imaging technology that achieves ccd image quality (based on signal-to-noise ratio and low-light sensitiv ity) while maintaining the inherent size, cost, and integration advantages of cmos. general description the aptina ? MT9P031 is a 1/2.5-inch cmos active- pixel digital image sensor wi th an active imaging pixel array of 2592h x 1944v. it incorporates sophisticated camera functions on-chip such as windowing, column and row skip mode, and snapshot mode. it is program- mable through a simple two-wire serial interface. parameter value optical format 1/2.5-inch (4:3) active imager size 5.70mm(h) x 4.28mm(v) 7.13mm diagonal active pixels 2592h x 1944v pixel size 2.2 x 2.2 m color filter array rgb bayer pattern shutter type global reset release (grr), snapshot only electronic rolling shutter (ers) maximum data rate/ master clock 96 mp/s at 96 mhz (2.8v i/o) 48 mp/s at 48 mhz (1.8v i/o) frame rate full resolution programmable up to 14 fps vga (640 x 480, with binning) programmable up to 53 fps adc resolution 12-bit, on-chip responsivity 1.4 v/lux-sec (550nm) pixel dynamic range 70.1db snr max 38.1db supply voltage i/o 1.7 ? 3.1v digital 1.7 ? 1.9v (1.8v nominal) analog 2.6 ? 3.1v (2.8v nominal) power consumption 381mw at 15 fps full resolution operating temperature C30c to +70c packaging 48-pin ilcc, die
pdf: 0548592346/source:9863314264 MT9P031_ds - rev. f 5/11 en 2 ?2005 aptina imaging corporation. all rights reserved. MT9P031: 1/2.5-inch 5mp digital image sensor general description
pdf: 0548592346/source:9863314264 MT9P031_ds - rev.f 5/11 en 3 ?2005 aptina imaging corporation. all rights reserved. MT9P031: 1/2.5-inch 5mp digital image sensor table of contents table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 functional overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 pixel data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 pixel array structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 default readout order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 output data format (default mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 readout sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 output data timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 lv and fv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 lv format options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 frame time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 frame rates at common resolution s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 serial bus description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 bus idle state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 start bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 stop bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 slave address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 data bit transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 acknowledge bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 no-acknowledge bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 two-wire serial interface sample write and read sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 16-bit write sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 16-bit read sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 hard reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 soft reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 power up and power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 pll-generated master clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 pll setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 standby and chip enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 full-array readout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 window control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 readout modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 subsampling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 skipping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 binning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 mirror . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 column mirror image. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 row mirror image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 maintaining a constant frame rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 synchronizing register writes to frame boundaries. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 image acquisition modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
pdf: 0548592346/source:9863314264 MT9P031_ds - rev.f 5/11 en 4 ?2005 aptina imaging corporation. all rights reserved. MT9P031: 1/2.5-inch 5mp digital image sensor table of contents electronic rolling shutter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 global reset release . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 exposure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 strobe control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 signal chain and datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 digital gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 analog black level calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 digital black level calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 test patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 classic test pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 color field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 vertical color bars. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 horizontal gradient . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 vertical gradient . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 diagonal gradient . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 walking 1s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 monochrome vertical bars . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 monochrome horizontal bars . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 spectral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 two-wire serial register interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 i/o timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 dc electrical characteri stics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 appendix a? power-on and standby timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
pdf: 0548592346/source:9863314264 MT9P031_dds - rev. f 5/11 en 5 ?2005 aptina imaging corporation. all rights reserved. MT9P031: 1/2.5-inch 5mp digital image sensor list of figures list of figures figure 1: block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 figure 2: typical configuration (connection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 figure 3: 48-pin ilcc 10 x 10 package pinout diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 figure 4: pixel array description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 figure 5: pixel color pattern detail (top right corner) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 figure 6: imaging a scene . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 figure 7: spatial illustration of image re adout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 figure 8: default pixel output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 9: lv format options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 figure 10: frame timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 figure 11: timing diagram showing a write to reg0x09 with the value 0x0284 . . . . . . . . . . . . . . . . . . . . . . . . .20 figure 12: timing diagram showing a read from reg0x09; return ed value 0x0284 . . . . . . . . . . . . . . . . . . . . . .20 figure 13: pll-generated master clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 figure 14: eight pixels in normal and column skip 2x readout modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 15: pixel readout (no skipping) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 16: pixel readout (column skip 2x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 17: pixel readout (row skip 2x). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 18: pixel readout (column skip 2x, row skip 2x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 19: pixel readout (column bin 2x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 figure 20: pixel readout (column bin 2x, ro w bin 2x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 figure 21: six pixels in normal and column mirror readout modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 figure 22: six rows in normal and row mi rror readout modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 figure 23: ers snapshot timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 figure 24: grr snapshot timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 figure 25: signal path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 figure 26: typical spectral char acteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 figure 27: cra vs. image height (7 deg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 figure 28: two-wire serial bus timing parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 figure 29: i/o timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 figure 30: 48-pin ilcc package outline drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 figure 31: power-on and standby timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
pdf: 0548592346/source:9863314264 mt9t031_ds - rev. f 5/11 en 1 ?2005 aptina imaging corporation. all rights reserved. MT9P031: 1/2.5-inch 5mp digital image sensor list of tables list of tables table 1: available part numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 2: key performance parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 3: pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 table 4: pixel type by column . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 table 5: pixel type by row . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 table 6: dark rows sampled as a function of row_bin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 table 7: dark columns sampled as a function of column_bin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 table 8: frame time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 table 9: hbmin values for row_bin vs. column_bin settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 table 10: standard resolutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 table 11: wide screen (16:9) resolutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 table 12: legal values for column_skip based on column_bin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 table 13: operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 table 14: strobe timepoints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 table 15: gain increment settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 table 16: test pattern modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 table 17: two-wire serial bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 table 18: i/o timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 table 19: dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 table 20: power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 table 21: absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
pdf: 09005aef81a4a477/source: 09005aef81a4a495 MT9P031_ds - rev. f 5/11 en 7 ?2005 aptina imaging corporation. all rights reserved. MT9P031: 1/2.5-inch 5mp digital image sensor general description general description the MT9P031 sensor can be operated in its default mode or programmed by the user for frame size, exposure, gain setting, and other parameters. the default mode outputs a full resolution image at 14 frames per second (fps). an on-chip analog-to-digital converter (adc) provides 12 bits pe r pixel. frame_valid (fv) and line_valid (lv) signals are output on dedicated pins, along with a pixel clock that is synchronous with valid data. the MT9P031produces extraordinarily clear, sharp digital pictures, and its ability to capture both continuous video and single frames makes it the perfect choice for a wide range of consumer and industrial applicat ions, including cell phones, digital still cameras, digital video cameras, and pc cameras. functional overview the MT9P031 is a progressive-scan sensor th at generates a stream of pixel data at a constant frame rate. it uses an on-chip, phas e-locked loop (pll) to generate all internal clocks from a single master input clock running between 6 and 27 mhz. the maximum pixel rate is 96 mp/s, corresponding to a cloc k rate of 96 mhz. figure 1 illustrates a block diagram of the sensor. figure 1: block diagram user interaction with the sensor is through the two-wire serial bus, which communi- cates with the array control, analog signal chai n, and digital signal chain. the core of the sensor is a 5mp active-pixel array. the ti ming and control circuitry sequences through the rows of the array, resetting and then read ing each row in turn. in the time interval between resetting a row and reading that row, the pixels in the row integrate incident light. the exposure is controlled by varying the time interval between reset and readout. once a row has been read, the data from th e columns is sequenced through an analog signal chain (providing offset correction and gain), and then through an adc. the output from the adc is a 12-bit value for each pixel in the array. the adc output passes through a digital processing signal chain (whi ch provides further data path corrections and applies digital gain). the pixel data are output at a rate of up to 96 mp/s, in addition to frame and line synchronization signals. pixel array 2752h x 2004v sclk s data s addr pixclk d out [11:0] lv fv strobe serial interface analog signal chain data path trigger extclk reset_bar standby_bar oe array control output
pdf: 09005aef81a4a477/source: 09005aef81a4a495 MT9P031_ds - rev. f 5/11 en 8 ?2005 aptina imaging corporation. all rights reserved. MT9P031: 1/2.5-inch 5mp digital image sensor functional overview figure 2: typical configuration (connection) note: 1. a resistor value of 1.5k is recommended, but may be greater for slower two-wire speed. 2. all power supplies should be adequately decoupled. 3. all d gnd pins must be tied together, as must all a gnd pins, all v dd _io pins, and all v dd pins. figure 3: 48-pin ilcc 10 x 10 package pinout diagram (top view) d out [11:0] pixclk fv lv strobe s addr reset_bar standby_bar sclk s data trigger v dd _io a gnd 3 test 1.5k 1 1.5k 1 v dd _io 2,3 v dd v dd 2,3 1f 10k rsvd d gnd 3 v dd _pll vaa_pix v aa v aa 2,3 oe to controller from controller master clock extclk 1 2 3 4 5 6 48474645 44 43 19 20 21 22 23 24 25 26 27 28 29 30 7 8 9 10 11 12 13 14 15 16 17 18 42 41 40 39 38 37 36 35 34 33 32 31 f rame_valid line_valid strobe d gnd v dd_ io v dd s addr standby_bar trigger reset_bar oe nc d out 8 d out 7 d out 6 v dd_ io d out 5 d out 4 d out 3 d out 2 d out 1 d out 0 pixclk extclk nc test test a gnd v aa v aa v dd_ pll d gnd nc nc nc nc rsvd s data sclk test a gnd vaa_pix vaa_pix v dd d gnd d out 11 d out 10 d out 9
pdf: 09005aef81a4a477/source: 09005aef81a4a495 MT9P031_ds - rev. f 5/11 en 9 ?2005 aptina imaging corporation. all rights reserved. MT9P031: 1/2.5-inch 5mp digital image sensor pixel data format pixel data format pixel array structure the MT9P031 pixel array consists of a 2 752-column by 2004-row matrix of pixels addressed by column and row. the address (column 0, row 0) represents the upper-right corner of the entire array, looking at the sensor, as shown in figure 4 on page 10. the array consists of a 2592-column by 1944-ro w active region in the center representing the default output image, surrounded by a boundary region (also active), surrounded by a border of dark pixels (see table 4 and ta ble 5). the boundary region can be used to avoid edge effects when doing color processing to achieve a 2592 x 1944 result image, while the optically black column and rows can be used to monitor the black level. table 3: pin description name type description reset_bar input when low, the MT9P031 asynchronously resets. when driven high, it resumes normal operation with all configuration registers set to factory defaults. extclk input external input clock. sclk input serial clock. pull to v dd _io with a 1.5 k resistor. oe input when high, the pixclk, d out , fv, lv, and strobe outputs enter a high-z. when driven low, normal operation resumes. standby_bar input standby. when low, the chip enters a low-power standby mode. it resumes normal operation when the pin is driven high. trigger input snapshot trigger. used to trigger one frame of output in snapshot modes, and to indicate the end of exposure in bulb exposure modes. s addr input serial address. when high, the MT9P031 responds to device id (ba) h . when low, it responds to serial device id (90) h . s data i/o serial data. pull to v dd _io with a 1.5 k resistor. pixclk output pixel clock. the d out , fv, lv, and strobe outputs should be captured on the falling edge of this signal. d out [11:0] output pixel data. pixel data is 12-bit. msb (d out 11) through lsb (d out 0) of each pixel, to be captured on the falling edge of pixclk. frame_valid output frame valid. driven high during active pixels and horizontal blanking of each frame and low during vertical blanking. line_valid output line valid. driven high with active pixels of each line and low during blanking periods. strobe output snapshot strobe. driven high when all pixels are exposing in snapshot modes. v dd supply digital supply voltage. nominally 1.8v. v dd _io supply io supply voltage. nominally 1.8 or 2.8v. d gnd supply digital ground. v aa supply analog supply voltage. nominally 2.8v. v aa _pix supply pixel supply voltage. nominally 2.8v, connected externally to v aa . a gnd supply analog ground. v dd _pll supply pll supply voltage. nominally 2.8v, connected externally to v aa . test tie to a gnd for normal device operation (factory use only). rsvd tie to d gnd for normal device operation (factory use only). nc no connect.
pdf: 09005aef81a4a477/source: 09005aef81a4a495 MT9P031_ds - rev. f 5/11 en 10 ?2005 aptina imaging corporation. all rights reserved. MT9P031: 1/2.5-inch 5mp digital image sensor pixel data format pixels are output in a bayer pattern format consisting of four ?colors??greenr, greenb, red, and blue (gr, gb, r, b)?representing three filter colors. when no mirror modes are enabled, the first row output alternates be tween gr and r pixels, and the second row output alternates between b and gb pixels. the gr and gb pixels have the same color filter, but they are treated as separate colors by the data path and analog signal chain. figure 4: pixel array description table 4: pixel type by column column pixel type 0C9 dark (10) 10C15 active boundary (6) 16C2607 active image (2592) 2608C2617 active boundary (10) 2618C2751 dark (134) table 5: pixel type by row row pixel type 0C 49 dark (50) 50C53 active boundary (4) 54C1997 active image (1944) 1998C2001 active boundary (3) 2002C2003 dark (2) (2751, 2003) 10 black columns 2 black rows 50 black rows (0,0) 134 black columns active image 2592 x 1944 active pixels 4 (16,54) 6 10 4
pdf: 09005aef81a4a477/source: 09005aef81a4a495 MT9P031_ds - rev. f 5/11 en 11 ?2005 aptina imaging corporation. all rights reserved. MT9P031: 1/2.5-inch 5mp digital image sensor pixel data format figure 5: pixel color pattern detail (top right corner) default readout order by convention, the sensor core pixel array is shown with pixel (0,0) in the top right corner (see figure 4). this reflects the actual layout of the array on the die. also, the first pixel data read out of the sensor in defa ult condition is that of pixel (16, 54). when the sensor is imaging, the active surface of the sensor faces the scene as shown in figure 5. when the image is read out of the se nsor, it is read one row at a time, with the rows and columns sequenced as shown in figure 6 on page 11. figure 6: imaging a scene first clear pixel (10,50) bla ck pixels column readout direction . . . . . . ... row readout direction gr b gr b gr b r gb r gb r gb gr b gr b gr b r gb r gb r gb gr b gr b gr b r gb r gb r gb gr b gr b gr b lens pixel (0,0) row readout order column readout order scene sensor (rear view)
pdf: 09005aef81a4a477/source: 09005aef81a4a495 MT9P031_ds - rev. f 5/11 en 12 ?2005 aptina imaging corporation. all rights reserved. MT9P031: 1/2.5-inch 5mp digital image sensor pixel data format output data format (default mode) the MT9P031 image data is read out in a progressive scan. va lid image data is surrounded by horizontal blanking and vert ical blanking, as shown in figure 7. lv is high during the shaded region of the figure. fv timing is described in ?output data timing? on page 14. figure 7: spatial illustration of image readout p 0,0 p 0,1 p 0,2 .....................................p 0,n-1 p 0,n p 1,0 p 1,1 p 1,2 .....................................p 1,n-1 p 1,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 p m-1,0 p m-1,1 .....................................p m-1,n-1 p m-1,n p m,0 p m,1 .....................................p m,n-1 p m,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 valid image horizontal blanking vertical blanking vertical/horizontal blanking
pdf: 09005aef81a4a477/source: 09005aef81a4a495 MT9P031_ds - rev. f 5/11 en 13 ?2005 aptina imaging corporation. all rights reserved. MT9P031: 1/2.5-inch 5mp digital image sensor pixel data format readout sequence typically, the readout window is set to a region including only active pixels. the user has the option of reading out dark regions of the ar ray, but if this is done, consideration must be given to how the sensor reads the dark regions for its own purposes. rows are read from the array in the following order: 1. dark rows: if show_dark_rows is set, or if manual_blc is clear, dark rows on the top of the array are read out. the set of rows sampled are adjusted based on the row_bin setting such that there are 8 rows after binning, as shown in the table 6. the row_skip setting is ignored for the dark row region. if show_dark_rows is clear and manual_blc is set, no dark rows are read from the array as part of this step, allowing all rows to be part of the active image. this does not change the frame time, as h dr is included in the vertical blank period. 2. active image: the rows defined by the row start, row size, bin, skip, and row mirror settings are read out. if this set of rows incl udes rows read out above, those rows are resampled, mean- ing that the data is invalid. columns are read out in the following order: 1. dark columns: if either show_dark_columns or row_blc is set, dark columns on the left side of the image are read out followed by those on the right side. the set of columns read is shown in table 7. the column_skip setting is ignored for the dark columns. if neither show_dark_columns nor row_blc is set, no dark columns are read, allow- ing all columns to be part of the active im age. this does not change the row time, as w dc is included in the vertical blank period. 2. active image: the columns defined by column start, column size, bin, skip, and column mirror set- tings are read out. if this set of columns includes the columns read out above, these columns are resampled, meaning the data is invalid. table 6: dark rows sampled as a function of row_bin row_bin h dr (dark rows after binning) 08 18 38 table 7: dark columns sampled as a function of column_bin column_bin w dc (dark columns after binning) 080 140 320
pdf: 09005aef81a4a477/source: 09005aef81a4a495 MT9P031_ds - rev. f 5/11 en 14 ?2005 aptina imaging corporation. all rights reserved. MT9P031: 1/2.5-inch 5mp digital image sensor output data timing output data timing the output images are divided into frames, which are further divided into lines. by default, the sensor produces 1944 rows of 2592 columns each. the fv and lv signals indicate the boundaries between frames and lines, respectively. pixclk can be used as a clock to latch the data. for each pixclk cy cle, one 12-bit pixel datum outputs on the d out pins. when both fv and lv are asserted, the pixel is valid. pixclk cycles that occur when fv is negated are called vertical blanking. pixclk cycles that occur when only lv is negated are called horizontal blanking. figure 8: default pixel output timing lv and fv the timing of the fv and lv outputs is closely related to the row time and the frame time. fv will be asserted for an integral number of row times, which will normally be equal to the height of the output image. if show_dark_rows is set, the dark sample rows will be output before the active image, and fv will be extended to include them. in this case, fv?s leading edge happens at time 0. lv will be asserted during the valid pixels of each row. the leading edge of lv will be offset from the leading edge of fv by 609 pixclks. if show_dark_columns is set, the dark columns will be output before the image pixels, and lv will be extended back to include them; in this case, the first pixel of th e active image still occu rs at the same posi- tion relative to the leading edge of fv. normally, lv will only be asserted if fv is asserted; this is configurable as described below. lv format options the default situation is for lv to be negated when fv is negated. the other option avail- able is shown in figure 9 on page 15. if continuous_lv is set, lv is asserted even when fv is not, with the same period and duty cycle. if xor_line_valid is set, but not continuous_line_valid, the resulting lv will be the xor of fv and the continuous lv. pixclk fv lv d out [11:0] p0 p1 p2 p3 p4 vertical blanking horiz blanking valid image data horiz blanking vertica l blanking pn
pdf: 09005aef81a4a477/source: 09005aef81a4a495 MT9P031_ds - rev. f 5/11 en 15 ?2005 aptina imaging corporation. all rights reserved. MT9P031: 1/2.5-inch 5mp digital image sensor output data timing figure 9: lv format options the timing of an entire frame is shown in figure 10. figure 10: frame timing default continuous lv xor lv fv lv fv lv fv lv lv column readout t row w row readout fv h t frame blanking region active image dark rows dark columns h dr w dc
pdf: 09005aef81a4a477/source: 09005aef81a4a495 MT9P031_ds - rev. f 5/11 en 16 ?2005 aptina imaging corporation. all rights reserved. MT9P031: 1/2.5-inch 5mp digital image sensor output data timing frame time the pixel clock (pixclk) represents the time needed to sample 1 pixel from the array, and is typically equal to 1 extclk period. the sensor outputs data at the maximum rate of 1 pixel per pixclk. one row time ( t row) is the period from the first pixel output in a row to the first pixel output in the next row. the row time and frame time are defined by equations in table 8. the minimum horizontal blanking (hb min ) values for various row_bin and column_bin settings are shown in table 9. table 8: frame time parameter name equation default timing at extclk=96mhz fps frame rate 1/ t frame 14 t frame frame time (h + max(vb, vb min )) t row 71.66ms t row row time 2 t pixclk x max(((w/2) + max(hb, hb min )), (41 + 346 x (row_bin+1) + 99)) 36.38 s w output image width 2 ceil((column_size + 1) / (2 (column_skip + 1))) 2592 pixclk h output image height 2 ceil((row_size + 1) / (2 (row_skip + 1))) 1944 rows sw shutter width max (1, (2 * 16 shutter_width_upper) + shutter_width_lower) 1943 rows hb horizontal blanking horizontal_blank + 1 1 pixclk vb vertical blanking vertical_blank + 1 26 rows hb min minimum horizontal blanking 346 (row_bin + 1) + 64 + (w dc / 2) 450 pixclk vb min minimum vertical blanking max (8, sw - h) + 1 9 rows t pixclk pixclk period 1/ f pixclk 10.42ns table 9: hb min values for row_bin vs. column_bin settings column_bin (w dc ) row_b in 013 0 450 430 420 1 796 776 766 3 1488 1468 1458
pdf: 09005aef81a4a477/source: 09005aef81a4a495 MT9P031_ds - rev. f 5/11 en 17 ?2005 aptina imaging corporation. all rights reserved. MT9P031: 1/2.5-inch 5mp digital image sensor output data timing frame rates at common resolutions table 10 and table 11 show examples of register settings to achieve common resolutions and their frame rates. frame rates are sh own both with subsampling enabled and disabled. note: 1. it is assumed that the minimum horizontal blanking and the minimum vertical blanking conditions are met, and that all other registers are set to default values. table 10: standard resolutions resolution frame rate sub- sampling mode column_si ze (r0x04) row_ size (r0x03) shutter_ width_ lower (r0x09) row_ bin (r0x22 [5:4]) row_ skip (r0x22 [2:0]) column_bin (r0x23 [5:4]) column_skip (r0x23 [2:0]) 2592 x 1944 (full resolution) 14 n/a 2591 1943 <1943 0 0 0 0 2048 x 1536 qxga 21 n/a 2047 1535 <1535 0 0 0 0 1600 x 1200 uxga 31 n/a 1599 1199 <1199 0 0 0 0 1280 x 1024 sxga 42 n/a 1279 1023 <1023 0 0 0 0 1024 x 768 xga 63 n/a 1023 767 <767 00 0 0 63 skipping 2047 1535 0 1 0 1 47 binning 2047 1535 1 1 1 1 800 x 600 svga 90 n/a 799 599 <599 00 0 0 90 skipping 1599 1199 0 1 0 1 65 binning 1599 1199 1 1 1 1 640 x 480 vga 123 n/a 639 479 <479 00 0 0 123 skipping 2559 1919 0 3 0 3 53 binning 2559 1919 3 3 3 3 table 11: wide screen (16:9) resolutions resolution frame rate sub- sampling mode column_si ze (r0x04) row_ size (r0x03) shutter_ width_ lower (r0x09) row_ bin (r0x22 [5:4]) row_ skip (r0x22 [2:0]) column_bin (r0x23 [5:4]) column_skip (r0x23 [2:0]) 1920 x 1080 hdtv 31 n/a 1919 1079 <1079 0 0 0 0 1280 x 720 hdtv 60 n/a 1279 719 <719 0 0 0 0 60 skipping 2559 1439 <719 0 1 0 1 45 binning 2559 1439 <719 1 1 1 1
pdf: 09005aef81a4a477/source: 09005aef81a4a495 MT9P031_ds - rev. f 5/11 en 18 ?2005 aptina imaging corporation. all rights reserved. MT9P031: 1/2.5-inch 5mp digital image sensor serial bus description serial bus description registers are written to and read from the mt 9p031 through the two-wire serial interface bus. the MT9P031 is a serial interface slave and is controlled by the serial clock (sclk), which is driven by the serial interface master. data is transferred into and out of the MT9P031 through the serial data (s data ) line. the s data line is pulled up to v dd _io off- chip by a 1.5k resistor. either the slave or master device can pull the s data line low? the serial interface protocol determines which device is allowed to pull the s data line down at any given time. protocol the two-wire serial defines several diffe rent transmission codes, as follows: 1. a start bit 2. the slave device 8-bit address 3. an (a no) acknowledge bit 4. an 8-bit message 5. a stop bit sequence a typical read or write sequence begins by the master sending a start bit. after the start bit, the master sends the slave device's 8-bit address. the last bit of the address determines if the request is a read or a wr ite, where a ?0? indicates a write and a ?1? indicates a read. the slave device acknowledges its address by sending an acknowledge bit back to the master. if the request is a write, the master then tr ansfers the 8-bit register address to which a write should take place. the slave sends an acknowledge bit to indicate that the register address has been received. the master then transfers the data 8 bits at a time, with the slave sending an acknowledge bit after each 8 bits. the MT9P031 uses 16-bit data for its internal registers, thus requiring two 8-bit transfers to write to one register. after 16 bits are transferred, the register ad dress is automatically incremented, so that the next 16 bits are written to the next regi ster address. the master stops writing by sending a start or stop bit. a typical read sequence is executed as follows. first the master sends the write-mode slave address and 8-bit register address, just as in the write request. the master then sends a start bit and the read-mode slave address. the master then clocks out the register data 8 bits at a time. the master sends an acknowledge bit after each 8-bit transfer. the register address is automatically-incremented after every 16 bits is trans- ferred. the data transfer is stopped when the master sends a no-acknowledge bit. bus idle state the bus is idle when both the data and cloc k lines are high. control of the bus is initi- ated with a start bit, and the bus is released with a stop bit. only the master can generate the start and stop bits. start bit the start bit is defined as a high-to-low transi tion of the data line while the clock line is high.
pdf: 09005aef81a4a477/source: 09005aef81a4a495 MT9P031_ds - rev. f 5/11 en 19 ?2005 aptina imaging corporation. all rights reserved. MT9P031: 1/2.5-inch 5mp digital image sensor serial bus description stop bit the stop bit is defined as a low-to-high transi tion of the data line while the clock line is high. slave address the 8-bit address of a two-wire serial interfac e device consists of 7 bits of address and 1 bit of direction. a ?0? in the lsb (least sign ificant bit) of the address indicates write mode (0xba), and a ?1? indicates read mode (0xbb). data bit transfer one data bit is transferred during each clock pulse. the serial interface clock pulse is provided by the master. the data must be stab le during the high period of the two-wire serial interface clock?it can only change wh en the serial clock is low. data is trans- ferred 8 bits at a time, foll owed by an acknowledge bit. acknowledge bit the master generates the acknowledge clock pu lse. the transmitter (which is the master when writing, or the slave when reading) re leases the data line, and the receiver indi- cates an acknowledge bit by pulling the data line low during the acknowledge clock pulse. no-acknowledge bit the no-acknowledge bit is generated when the data line is not pulled down by the receiver during the acknowledge clock pulse. a no-acknowledge bit is used to terminate a read sequence.
pdf: 09005aef81a4a477/source: 09005aef81a4a495 MT9P031_ds - rev. f 5/11 en 20 ?2005 aptina imaging corporation. all rights reserved. MT9P031: 1/2.5-inch 5mp digital image sensor two-wire serial interface sample write and read sequences two-wire serial interface sample write and read sequences 16-bit write sequence a typical write sequence for writing 16 bits to a register is shown in figure 11. a start bit given by the master, followed by the write address, starts the sequence. the image sensor then gives an acknowledge bit and expects the re gister address to come first, followed by the 16-bit data. after each 8-bit transfer, th e image sensor gives an acknowledge bit. all 16 bits must be written before the register is updated. after 16 bits are transferred, the register address is automatically incremented so that the next 16 bits are written to the next register. the master stops writ ing by sending a start or stop bit. figure 11: timing diagram showing a write to reg0x09 with the value 0x0284 16-bit read sequence a typical read sequence is shown in figure 12. first the master has to write the register address, as in a write sequence. then a st art bit and the read address specify that a read is about to happen from the register. the master then clocks out the register data 8 bits at a time. the master sends an acknowled ge bit after each 8-bit transfer. the register address should be incremented after every 16 bits is transferred. the data transfer is stopped when the master sends a no-acknowledge bit. figure 12: timing diagram showing a read from reg0x09; returned value 0x0284 sclk s data start ack 0xba addr ack ack ack stop reg0x09 1000 0100 0000 0010 sclk s data start ack 0xba addr 0xbb addr 0000 0010 reg0x09 ack ack ack stop 1000 0100 nack start
pdf: 09005aef81a4a477/source: 09005aef81a4a495 MT9P031_ds - rev. f 5/11 en 21 ?2005 aptina imaging corporation. all rights reserved. MT9P031: 1/2.5-inch 5mp digital image sensor features features reset the MT9P031 may be reset by using reset_ bar (active low) or the reset register. hard reset assert (low) reset_bar, it is not necessary to clock the device. all registers return to the factory defaults. when the pin is nega ted (high), the chip resumes normal opera- tion. soft reset set the reset register field to ?1? (r0x0d[0] = 1). all registers except the following will be reset: ?chip_enable ? synchronize_changes ?reset ? use_pll ?power_pll ? pll_m_factor ? pll_n_divider ?pll_p1_divider when the field is returned to ?0,? the chip resumes normal operation. power up and power down when first powering on the MT9P031, follow this sequence: 1. ensure reset_bar is asserted (low). 2. bring up the supplies. if both the analog and the digital supplies cannot be brought up simultaneously, ensure the digital supply comes up first. 3. negate reset_bar (high) to bring up the sensor. when powering down, be sure to follow this sequence to ensure that i/os do not load any buses that they are connected to. 1. assert reset_bar. 2. remove the supplies. clocks the MT9P031 requires one clock (extclk), whic h is nominally 96 mhz. by default, this results in pixels being output on the d out pins at a maximum data rate of 96 mp/s. with v dd _io = 1.8v, maximum master clock and maximum data rate become 48 mhz and 48 mp/s, respectively. the extclk clock can be divided down internally by setting divide_pixel_clock to a non-zero value. this slows down the operation of the chip as though extclk had been divided externally. f extclk if divide_pixel_clock = 0 f pixclk= { f extclk / (2 divide_pixel_clock) otherwise
pdf: 09005aef81a4a477/source: 09005aef81a4a495 MT9P031_ds - rev. f 5/11 en 22 ?2005 aptina imaging corporation. all rights reserved. MT9P031: 1/2.5-inch 5mp digital image sensor features the d out , lv, fv, and strobe outputs are launched on the rising edge of pixclk, and should be captured on the falling edge of pixclk. the specific relationship of pixclk to these other outputs can be adjusted in two ways . if invert_pixel_clock is set, the sense of pixclk is inverted from that shown in figure 8 on page 14. in addition, if the pixel clock has been divided by divide_pixel_clock, it can be shifted relative to the other outputs by setting shift_pixel_clock. pll-generated master clock the pll contains a prescaler to divide th e input clock applied on extclk, a vco to multiply the prescaler output, and another divider stage to generate the output clock. the clocking structure is shown in figure 13. pll control registers can be programmed to generate desired ma ster clock frequency. note: the pll control registers must be programm ed while the sensor is in the software standby state. the effect of programming the pll divisors while the sensor is in the streaming state is undefined. figure 13: pll-generated master clock pll setup the MT9P031 has a pll which can be used to generate the pixel clock internally. to use the pll: 1. bring the MT9P031 up as normal, make sure that f extclk is between 6 and 27 mhz and then power on the pll by setting power_pll (r0x10[0] = 1). 2. set pll_m_factor, pll_n_divider, and pll_p1_divider based on the desired input ( f extclk) and output ( f pixclk) frequencies. determine the m, n, and p1 values to achieve the desired f pixclk using this formula: f pixclk = ( f extclk m) / (n p1) where m = pll_m_factor n = pll_n_divider + 1 p1 = pll_p1_divider + 1 note: if p1 is odd (that is, pll_p1_divider is ev en), the duty cycle of the internal system clock will not be 50:50. in this case, it is impo rtant that either a slow er clock is used or all clock enable bits are set in r101. extclk pll output clock pll_n_divider +1 pre pll div (pfd) pll input clock pll multiplier (vco) pll output div 1 pll_p1_divider +1 pll_m_factor sysclk (pixclk) n m p1
pdf: 09005aef81a4a477/source: 09005aef81a4a495 MT9P031_ds - rev. f 5/11 en 23 ?2005 aptina imaging corporation. all rights reserved. MT9P031: 1/2.5-inch 5mp digital image sensor features 2 mhz < f extclk / n < 13.5 mhz 180 mhz < ( f extclk m) / n < 360 mhz it is desirable to keep ( f extclk / n) as large as possible within the limits. also, "m" must be between 16 and 255, inclusive. 3. wait 1ms to ensure that the vco has locked. 4. set use_pll (r0x10[1] = 1) to switch from extclk to the pll-generated clock. standby and chip enable the MT9P031 can be put in a low-power standby state by either method below: 1. hard standby: by pulling standby_bar low, or 2. soft standby: by clearing the chip_enable register field (r0x07[1] = 0). when the sensor is put in standby, all intern al clocks are gated, an d analog circuitry is put in a state that it draws minimal power. th e two wire serial interface is still active. if the sensor was in continuous mode when put in standby, it resumes from where it was when standby was deactivated. naturally, th is frame and the next frame are corrupted, though the sensor itself does not realize this . as this could affect automatic black level calibration, it is recommended that either the chip be paused (by setting restart_pause) before being put in standby mode, or it be re started (setting restart) upon resumption of operation. entering soft standby reg= 0x0b, 0x0002 reg= 0x0b, 0x0003 reg= 0x07, 0x1f82 reg= 0x07, 0x1f80 reg= 0x0b, 0x0001 leaving soft standby reg= 0x0b, 0x0002 reg= 0x0b, 0x0003 reg= 0x07, 0x1f80 reg= 0x07, 0x1f82 reg= 0x0b, 0x0001 for maximum power savings in standby mode, extclk should not be toggling. when standby mode is entered, either by clearing chip_enable or by asserting standby_bar, the pll is disabled automatically or powered down. it must be manu- ally re-enabled when leaving standby as needed.
pdf: 09005aef81a4a477/source: 09005aef81a4a495 MT9P031_ds - rev. f 5/11 en 24 ?2005 aptina imaging corporation. all rights reserved. MT9P031: 1/2.5-inch 5mp digital image sensor features full-array readout the entire array, including dark pixels, can be read out without digital processing or automatic black level adjustments. this can be accomplished as follows: 1. set row_start and column_start to 0. 2. set row_size to 2003. 3. set column_size to 2751. 4. set manual_blc to 1. 5. set row_blc to 0. 6. set row_black_default_offset to 0. 7. set show_dark_rows and show_dark_columns to 0. if automatic analog (coarse) blc is desired, but no digital processing, modify the above settings as follows: 1. set row_start to 12. 2. set row_size to 1993. 3. set manual_blc to 0. these settings result in the same array layout as above, but only 22 dark rows are avail- able at the top of the array; the first eight are used in the black level algorithm, and there should be a two-row buffer between the black region and the active region. window control the output image window of the pixel (the fov) is defined by four register fields. column_start and row_start define the x and y coordinates of the upper-left corner of the fov. column_size defines the width of th e fov, and row_size defines the height of the fov in array pixels. the column_start and row_start fields must be set to an even number. the column_size and row_size fields must be set to odd numbers (resulting in an even size for the fov). the row_start register should be set no lower than 12 if either manual_blc is clear or show_dark_rows is set. if no special resolution modes are set (see be low), the width of the output image, w, is ( column_size + 1) and the height, h, is (row_size + 1) . readout modes subsampling by default, the resolution of the output ima ge is the full width and height of the fov as defined in ?window control?. the output resolution can be reduced by two methods: skipping and binning. row and column skip modes use subsampling to reduce the output resolution without reducing fov. the MT9P031 also has row an d column binning modes, which can reduce the impact of aliasing introduced by the use of skip modes. this is achieved by the aver- aging of 2 or 3 adjacent rows and columns (a djacent same-color pixels). both 2x and 4x binning modes are supported. rows and columns can be binned independently.
pdf: 09005aef81a4a477/source: 09005aef81a4a495 MT9P031_ds - rev. f 5/11 en 25 ?2005 aptina imaging corporation. all rights reserved. MT9P031: 1/2.5-inch 5mp digital image sensor features skipping skipping reduces resolution by using only selected pixels from the fov in the output image. in skip mode, entire rows and columns of pixels are not sampled, resulting in a lower resolution output image. a skip 2x mo de skips one bayer pair of pixels for every pair output. skip 3x skips two pairs for ea ch one pair output. rows and columns are always read out in pairs. if skip 2x mode is enabled with othe rwise default sensor settings, the columns in the output image co rrespond to the pixel array columns 16, 17, 20, 21, 24, 25... . figure 14: eight pixels in normal and column skip 2x readout modes skipping can be enabled separately for rows and columns. to enable skip mode, set either or both of row_skip and column_skip to the number of pixel pairs that should be skipped for each pair used in the output im age. for example, to set column skip 2x mode, set column_skip to ?1.? the size of the output image is reduced by the skip mode as shown in the following two equations: w = 2 x ceil((column_size + 1) / (2 x (column_skip + 1))) h = 2 x ceil((row_size + 1) / (2 x (row_skip + 1))) figure 15: pixel readout (no skipping) g0 [11:0] r0 [11:0] g1 [11:0] r1 [11:0] g2 [11:0] r2 [11:0] g3 [11:0] r3 [11:0] g0 [11:0] r0 [11:0] g2 [11:0] r2 [11:0] lv normal readout d out [11:0] lv column skip 2x readout d out [11:0] x incrementing y in crementing
pdf: 09005aef81a4a477/source: 09005aef81a4a495 MT9P031_ds - rev. f 5/11 en 26 ?2005 aptina imaging corporation. all rights reserved. MT9P031: 1/2.5-inch 5mp digital image sensor features figure 16: pixel readout (column skip 2x) figure 17: pixel readout (row skip 2x) figure 18: pixel readout (column skip 2x, row skip 2x) x incrementing y incrementing x incrementing y incrementing x incrementing y incrementing
pdf: 09005aef81a4a477/source: 09005aef81a4a495 MT9P031_ds - rev. f 5/11 en 27 ?2005 aptina imaging corporation. all rights reserved. MT9P031: 1/2.5-inch 5mp digital image sensor features binning binning reduces resolution by combining adjacent same-color imager pixels to produce one output pixel. all of the pixels in the fo v contribute to the output image in bin mode. this can result in a more pleasing output image with reduced subsampling artifacts. it also improves low-light performance. for columns, the combination step can be either an averaging or summing operation. dependin g on lighting conditions, one or the other may be desirable. in low-light conditions, summing produces a gain roughly equivalent to the column bin factor. column summing may be enabled by setting column_sum. binning works in conjunction with skipping. pi xels that would be skipped because of the column_skip and row_skip settings can be averaged instead by setting column_bin and row_bin to the number of neighbor pixels to be averaged with each output pixel. for example, to set bin 2x mode, set column_skip and column_bin to 1. additionally, column_start must be a multiple of (2 * (column_bin + 1)) and row_start must be a multiple of (2 * (row_bin + 1)). only certain combinations of bi nning and skipping are allowed. these are shown in table 12. if an illegal skip value is selected for a bin mode, a legal value is selected instead. note: ensure that column_start (r0x02) is set in the form shown below, where n is an integer: bin mode is illustrated in figure 19 and figure 20. figure 19: pixel readout (column bin 2x) table 12: legal values for column_skip based on column_bin column_bin legal values for column_skip 0 (no binning) 0, 1, 2, 3, 4, 5, 6 1 (bin 2x) 1, 3, 5 3 (bin 4x) 3 mirror column = 0 mirror column = 1 no bin 4n 4n + 2 bin 2x 8n 8n + 4 bin 4x 16n 16n + 8 x incrementing y increm enting
pdf: 09005aef81a4a477/source: 09005aef81a4a495 MT9P031_ds - rev. f 5/11 en 28 ?2005 aptina imaging corporation. all rights reserved. MT9P031: 1/2.5-inch 5mp digital image sensor features figure 20: pixel readout (column bin 2x, row bin 2x) mirror column mirror image by setting r0x20[14] = 1, the readout order of the columns is reversed, as shown in figure 21. the starting color, thus bayer pattern, is preserved when mirroring the columns. figure 21: six pixels in normal and column mirror readout modes row mirror image by setting r0x20[15] = 1, the readout order of the rows is reversed as shown in figure 22. the starting color, thus bayer pattern, is preserved when mirroring the rows. figure 22: six rows in normal and row mirror readout modes x incrementing y incre menting g0[11:0] r0[11:0] g1[11:0] r1[11:0] g2[11:0] r2[11:0] r2[11:0] g2[11:0] r1[11:0] g1[11:0] r0[11:0] g0[11:0] d out [11:0] lv normal readout d out [11:0] reverse readout row0 [11:0] row1 [11:0] row2 [11:0] row3 [11:0] row4 [11:0] row5 [11:0] row5 [11:0] row4 [11:0] row3 [11:0] row2 [11:0] row1 [11:0] row0 [11:0] d out [11:0] fv normal readout d out [11:0] reverse readout
pdf: 09005aef81a4a477/source: 09005aef81a4a495 MT9P031_ds - rev. f 5/11 en 29 ?2005 aptina imaging corporation. all rights reserved. MT9P031: 1/2.5-inch 5mp digital image sensor features by default, active pixels in the resulting image are output in row-major order (an entire row is output before the next row is begun), from lowest row/column number to highest. if desired, the output (and sampling) order of the rows and columns can be reversed. this affects only pixels in the active region defined above, not any pixels read out as dark rows or dark columns. when the readout direct ion is reversed, the color order is reversed as well (red, green, red, and so on, instead of green, red, green, and so on, for example). if row binning is combined with row mirroring, the binning is still done in the positive direction. therefore, if the first output ro w in bin 2x + row mirror was 1997, pixels on rows 1997 and 1999 would be averaged togeth er. the next pixel output would be from rows 1996 and 1998, followed by the average of 1993 and 1995. for column mirroring plus binni ng, the span of pixels used should be the same as with non-mirror mode. maintaining a constant frame rate maintaining a constant frame rate while contin uing to have the ability to adjust certain parameters is the desired scenario. this is not always possible, however, because register updates are synchronized to the read pointer, and the shutter pointer for a frame is usually active during the readout of the prev ious frame. therefore, any register changes that could affect the row time or the set of rows sampled causes the shutter pointer to start over at the beginning of the next frame. by default, the following register fields caus e a "bubble" in the output rate (that is, the vertical blank increases for one frame) if they are written in continuous mode, even if the new value would not change the resulting frame rate: ? row_start ?row_size ?column_size ?horizontal_blank ?vertical_blank ? shutter_delay ? mirror_row ? row_bin ?row_skip ?column_skip the size of this bubble is (sw t row), calculating the row time according to the new settings. the shutter_width_lower and shutter_widt h_upper fields may be written without causing a bubble in the output rate under certain circumstances. because the shutter sequence for the next frame often is active du ring the output of the current frame, this would not be possible without special provisio ns in the hardware. writes to these regis- ters take effect two frames after the frame they are written, which allows the shutter width to increase without interrupting the ou tput or producing a corrupt frame (as long as the change in shutter width does not affect the frame time).
pdf: 09005aef81a4a477/source: 09005aef81a4a495 MT9P031_ds - rev. f 5/11 en 30 ?2005 aptina imaging corporation. all rights reserved. MT9P031: 1/2.5-inch 5mp digital image sensor features synchronizing register writ es to frame boundaries changes to most register fields that affect th e size or brightness of an image take effect on the frame after the one during which they are written. these fields are noted as ?synchronized to frame boundaries? in table 12 of the register reference. to ensure that a register update takes effect on the next frame, the write operation must be completed after the leading edge of fv and before the trailing edge of fv. as a special case, in snapshot modes (see ?ope rating modes? on page 32), register writes that occur after fv but before the next trigge r will take effect immediately on the next frame, as if there had been a restart. howeve r, if the trigger for the next frame in ers snapshot mode occurs during fv, register writes take effect as with continuous mode. additional control over the timing of register updates can be achieved by using synchronize_changes. if this bit is set, writes to certain register fields that affect the brightness of the output image do not take effect immediately. instead, the new value is remembered internally. when synchronize_changes is cleared, all the updates simulta- neously take effect on the next frame (as if they had all been written the instant synchronize_changes was cleared). register fiel ds affected by this bit are identified in table 13 of the register reference. fields not identified as being frame-synchronized or affected by synchronize_changes are updated immediately after the register writ e is completed. the effect of these regis- ters on the next frame can be difficult to predict if they affect the shutter pointer. restart to restart the MT9P031 at any time during the operation of the sensor, write a ?1? to the restart register (r0x0b[0] = 1). this has two e ffects: first, the current frame is interrupted immediately. second, an y writes to frame-synchronized registers and the shutter width registers take effect immediately, and a new frame starts (in continuous mode). register updates being held by synchronize_changes do not take effect until that bit is cleared. the current row and one following row complete before the new frame is started, so the time between issuing the restart and the begi nning of the next frame can vary by about t row. if pause_restart is set, rather than immedi ately beginning the next frame after a restart in continuous mode, the sensor pauses at the beginning of the next frame until pause_restart is cleared. this can be used to achieve a deterministic time period from clearing the pause_restart bit to the beginni ng of the first frame, meaning that the controller does not need to be tightly synchronized to lv or fv. note: when pause_restart is cleared, be sure to le ave restart set to ?1? for proper operation. the restart bit will be cleared automatically by the device.
pdf: 09005aef81a4a477/source: 09005aef81a4a495 MT9P031_ds - rev. f 5/11 en 31 ?2005 aptina imaging corporation. all rights reserved. MT9P031: 1/2.5-inch 5mp digital image sensor features image acquisition modes the MT9P031 supports two image acquisition modes (shutter types) (see ?operating modes? on page 32), electronic rolling shutter and global reset release. electronic rolling shutter the ers modes take pictures by scanning th e rows of the sensor twice in the order described in ?full-array readout? on page 24. on the first scan, each row is released from reset, starting the exposure. on the second scan, the row is sampled, processed, and returned to the reset state. the exposure for any row is therefore the time between the first and second scans. each row is exposed for the same duration, but at slightly different point in time, which can cause a shear in moving subjects. whenever the mode is changed to an ers mode (even from another ers mode), and before the first frame following reset, there is an anti-blooming sequence where all rows are placed in reset. this sequence must complete before continuous readout begins. this delay is: t allreset = 16 2004 t aclk global reset release the grr modes attempt to address the shearing effect by starting all rows' exposures at the same time. instead of the first scan us ed in ers mode, the reset to each row is released simultaneously. the second scan oc curs as normal, so th e exposure time for each row would different. typically, an external mechanical shutter would be used to stop the exposure of all rows simultaneously. in grr modes, there is a startup overhead be fore each frame as all rows are initially placed in the reset state ( t allreset). unlike ers mode, this delay always occurs before each frame. however, it occurs as soon as possible after the preceding frame, so typically the time from trigger to the start of exposure does not include this delay. to ensure that this is the case, the first trigger must occur no sooner than t allreset after the previous frame is read out. exposure the nominal exposure time, t exp, is the effective shutter time in ers modes, and is defined by the shutter width, sw, and the shut ter overhead, so, which includes the effect of shutter_delay. exposure time for other modes is defined relative to this time. increasing shutter_delay (sd) decreases the exposure time. exposure times are typically specified in units of row time, although it is possible to fine-tune exposures in units of t aclks (where t aclk is 2 * t pixclk). t exp = sw t row ? so 2 t pixclk where: sw = max(1, (2 * 16 shutter_width_upper) + shutter_width_lower) so = 208 (row_bin + 1) + 98 + min(sd, sdmax) ? 94 sd = shutter_delay + 1 sdmax = 1232; if sw < 3 1504, otherwise
pdf: 09005aef81a4a477/source: 09005aef81a4a495 MT9P031_ds - rev. f 5/11 en 32 ?2005 aptina imaging corporation. all rights reserved. MT9P031: 1/2.5-inch 5mp digital image sensor features the exposure time is calculated by determin ing the reset time of each pixel row (with time 0 being the start of the first row time), and subtracting it from the sample time. under normal conditions in ers modes, ever y pixel should end up with the same expo- sure time. in global shutter release modes, or in row binning modes, the exposure times of individual pixels can vary. in global shutter release modes (described later), exposure time starts simultaneously for all rows, but still ends as defined above. in a real system, the exposure would be stopped by a mechanical shutter, which would effectively stop the exposure to all rows simultaneously. each output row's exposure time will differ by t row from the previous row because this specification does not cons ider the effect of an external shutter . global shutter modes also introduce a constant added to the shutter time for each row, because the exposure starts during the global shutter sequence, and not during any row's shutter sequence. for each additional row in a row bin, this offset will increase by the length of the shutter sequence. in bulb_exposure modes (see details in table 13), the exposure time is determined by the width of the trigger pulse rather than the shutter width registers. in ers bulb mode, it is still a multiple of row times, and the shutter overhead equation still applies. in grr bulb mode, the exposure time is granular to aclks, and shutter overhead (and thus shutter_delay) has no effect. operating modes in default operating mode, the MT9P031 cont inuously samples and outputs frames. it can be put in "snapshot" or triggered mode by setting snapshot, which means that it samples and outputs a frame only when triggered. to leave snapshot mode, it is neces- sary to first clear snapshot then issue a restart. when in snapshot mode, the sensor can use the ers or the grr. the exposure can be controlled as normal, with the shutter_width_lower and shutter_width_upper regis- ters, or it can be controlled using the external trigger signal. the various operating modes are summarized in table 13. note: in ers bulb mode, sw must be greater than 4 (use trigger wider than t row * 4). all operating modes share a common set of operations: 1. wait for the first trigger, then start the exposure. 2. wait for the second trigger, then start the readout. table 13: operating modes mode settings description ers continuous default frames are output continuously at the frame rate defined by t frame. ers is used, and the exposure time is electronically controlled to be t exp. ers snapshot snapshot = 1 frames are output one at a time, with each frame initiated by a trigger. ers is used, and the exposure time is electronically controlled to be t exp. ers bulb snapshot = 1; bulb_exposure = 1 frames are output one at a time, with each frame's exposure initiated by a trigger. ers is used. end of exposure and readout are initiated by a second trigger. grr snapshot snapshot = 1; global_reset = 1 frames are output one at a time, with each frame initiated by a trigger. grr is used. readout is electronically triggered based on sw. grr bulb snapshot = 1; bulb_exposure = 1; global_reset = 1 frames are output one at a time, with each frame initiated by a trigger. grr is used. readout is initiated by a second trigger.
pdf: 09005aef81a4a477/source: 09005aef81a4a495 MT9P031_ds - rev. f 5/11 en 33 ?2005 aptina imaging corporation. all rights reserved. MT9P031: 1/2.5-inch 5mp digital image sensor features the first trigger is by default automatic, prod ucing continuous images. if snapshot is set, the first trigger can either be a low level on the trigger pin or writing a ?1? to the trigger register field. if invert_trigger is set, the first trigger is a high level on trigger pin or a ?1? written to trigger register field. because trigger is level-sensitive, multiple frames can be output (with a frame rate of t frame) by holding trigger pin at the trig- gering level. the second trigger is also normally automatic, and generally occurs sw row times after the exposure is started. if bulb_exposure is set, the second trigger can either be a high level on trigger or a write to restart. if invert_trigger is set, the second trigger is a low level on trigger (or a restart). in bulb modes, the minimum possible exposure time depends on the mechanical shutter used. after one frame has been output, the chip will reset step 1, above, eventually waiting for the first trigger again. the next tri gger may be issued after ((vb - 8) x t row ) in ers modes or t allrest in grr modes. the choice of shutter type is made by global_reset. if it is set, the grr shutter is used; otherwise, ers is used. the two shutters are described in ?electronic rolling shutter? on page 31 and ?global reset release? on page 31. the default ers continuous mode is shown in figure 8 on page 14. figure 23 shows default signal timing for ers snapshot mode s, while figure 24 on page 34 shows default signal timing for grr snapshot modes. figure 23: ers snapshot timing trigger strobe fv lv d out trigger strobe fv lv d out (a) ers snapshot (b) ers bulb tt1 tse tsw tt2 (h + vb) x t row (h + vb) x t row 8 x t row t row t row 8 x t row t row 8 x t row t row sw x t row 8 x t row first row exposure second row exposure first row exposure second row exposure sw x t row tt1 tsw tt2 tse
pdf: 09005aef81a4a477/source: 09005aef81a4a495 MT9P031_ds - rev. f 5/11 en 34 ?2005 aptina imaging corporation. all rights reserved. MT9P031: 1/2.5-inch 5mp digital image sensor features figure 24: grr snapshot timing strobe control to support synchronization of the exposure with external events such as a flash or mechanical shutter, the mt9p0 31 produces a strobe output. by default, this signal is asserted for approximately the time that all rows are simultaneously exposing, minus the vertical blanking time, as shown in figure 23 on page 33 and figure 24. also indicated in these figures are the leading and trailing edges of strobe, which an be configured to occur at one of several timepoints. the lead ing edge of strobe occurs at strobe_start, and the trailing edge at strobe_end, whic h are set to codes described in table 14. if strobe_start and strobe_end are set to the same timepoint, the strobe is a t row wide pulse starting at the strobe_start ti mepoint. if the settings are such that the strobe would occur after the trailing edge of fv, the strobe may be only t ackl wide; however, because there is no concept of a row at that time. the sense of the strobe table 14: strobe timepoints symbol timepoint code tt1 trigger 1 (start of shutter scan) C tse start of exposure (all rows simultaneously exposing) offset by vb 1 tsw end of shutter width (expiration of the internal shutter width counter) 2 tt2 trigger 2 (start of readout scan) 3 trigger strobe fv lv d out trigger strobe fv lv d out (a) grr snapshot (b) grr bulb tse tsw tt2 tsw tse tt2 vb x t row + 2000 x t aclk t row 8 x t row t row 8 x t row first row exposure first row exposure vb x t row + 2000 x t aclk second row exposure second row exposure sw x t row + 2000 x t aclk sw x t row + 2000 x t aclk tt1 tt1
pdf: 09005aef81a4a477/source: 09005aef81a4a495 MT9P031_ds - rev. f 5/11 en 35 ?2005 aptina imaging corporation. all rights reserved. MT9P031: 1/2.5-inch 5mp digital image sensor features signal can be inverted by setti ng invert_strobe (r0x1e[5] = 1. to use strobe as a flash in snapshot modes or with mech anical shutter, set the stro be_enable register bit field r0x1e[4] = 1. signal chain and datapath the signal chain and datapath are shown in figure 25. each color is processed indepen- dently, including separate gain and offset settings. voltages sampled from the pixel array are first passed through an analog gain stag e, which can produce gain factors between 1 and 8. an analog offset is then applied, and the signal is sent thro ugh a 12-bit analog-to- digital converter. in the digital space, a digital gain factor of between 1 and 16 is applied, and then a digital offset of between ?2048 an d 2047 is added. the resulting 12-bit pixel value is then output on the d out [11:0] ports. the analog offset applied is determined au tomatically by the black level calibration algorithm, which attempts to shift the output of the analog signal chain so that black is at a particular level. the digital offset is a fine-tuning of the analog offset. figure 25: signal path gain there are two types of gain supported: analog gain and digital gain. combined, gains of between 1 and 128 are possible. the recommended gain settings are shown in table 15. note: analog gain should be maximized before applying digital gain. the combined gain for a color c is given by: g c = ag c x dg c . table 15: gain increment settings gain range increments digital gain analog multipier analog gain 1C 4 0.125 0 0 8C32 4.25C8 0.25 0 1 17C32 9C128 1 1C120 1 32 pixel voltage digital gain analog gain digital datapath x + analog signal chain x + digital offset correction black level calibration d out [11: 0] adc analog offset
pdf: 09005aef81a4a477/source: 09005aef81a4a495 MT9P031_ds - rev. f 5/11 en 36 ?2005 aptina imaging corporation. all rights reserved. MT9P031: 1/2.5-inch 5mp digital image sensor features analog gain the analog gain is specified independently for each color channel. there are two components, the gain and the multiplier. the gain is specified by green1_analog_gain, red_analog_gain, blue_analog_gain, and green2_analog_gain in steps of 0.125. the analog multiplier is specified by green1 _analog_multiplier, red_analog_multiplier, blue_analog_multiplier, and green2_analog_m ultiplier. these combine to form the analog gain for a given color c as shown in this equation: ag c = (1 + c_analog_multiplie r) (c_analog_gain / 8) the gain component can range from 0 to 7.875 in steps of 0.125, and the multiplier component can be either 0 or 1 (resulting in a mu ltiplier of 1 or 2). however, it is best to keep the "gain" component between 1 and 4 fo r the best noise performance, and use the multiplier for gains between 4 and 8. digital gain the digital gain is specified independently for each color channel in steps of 0.125. it is controlled by the register fields gr een1_digital_gain, red_digital_gain, blue_digital_gain, and green2_digital_gain. the digital gain for a color c is given by: dg c = 1 + (c_digital_gain / 8) offset the MT9P031sensor can apply an offset or shif t to the image data in a number of ways. an analog offset can be applied on a color-wise basis to the pixel voltage as it enters the adc. this makes it possible to adjust for the offset introduced in the pixel sampling and gain stages to be removed, centering the resu lting voltage swing in the adc's range. this offset can be automatically determined by the sensor using the automatic black level calibration (blc) circuit, or it can be set manual ly by the user. it is a fairly coarse adjust- ment, with adjustment step sizes of 4 to 8 lsbs. digital offset is also added on a color-wise and line-wise basis to fine tune the black level of the output image. this offset is based on an average black level taken from each row's dark columns, and is automatically determined by the digital row-wise black level cali- bration (rblc) circuit. if the rblc circuit is not used, a user de fined offset can be applied instead. this offset has a resolution of 1 lsbs. a digital offset is added on a color-wise basis to account for channel offsets that can be introduced due to "even" and "odd" pixels of the same color going through a slightly different adc chain. this offset is automatically determined based on dark row data, but it can also be manually set. analog black level calibration the MT9P031 black level calibration circuitry provides a feedback control system since adjustments to the analog offset are imprecise by nature. the goal is that within the dark row region of any supported output image si ze, the offset should have been adjusted such that the average black level falls within the specified target thresholds. the analog offsets normally need a major ad justment only when leaving the reset state or when there has been a change to a color' s analog gain. factors like shutter width and temperature have lower-order impact, and generally only require a minor adjustment to the analog offsets. the MT9P031 has various ca libration modes to keep the system stable while still supporting the need for ra pid offset adjustments when necessary. the two basic steps of black level calibration are:
pdf: 09005aef81a4a477/source: 09005aef81a4a495 MT9P031_ds - rev. f 5/11 en 37 ?2005 aptina imaging corporation. all rights reserved. MT9P031: 1/2.5-inch 5mp digital image sensor features 1. take a sample. 2. if necessary, adjust the analog offset. black level calibration is normally done sepa rately for each color channel, and different channels can use different sample or adjustment methods at the same time. however, because both green1 and green2 pixels go through the same signal chain, and red and blue pixels likewise go through the same signal chain, it is expected that the chosen offset for these pairs should be the same as long as the gains are the same. if lock_green_calibration is set, and (gre en1_analog_gain = green2_analog_gain) and (green1_analog_multiplier = green2_analog_multiplier), the calculated or user-speci- fied green1_offset is used for both green channels. similarly, if lock_red/ blue_calibration is set, and (red_analog_gain = blue_analog_gain) and (red_analog_multiplier = blue_analog_multiplier), the calculated or user-specified red_offset is used for both the red and blue channels. the current values of the offsets can be read from the green1_offset, red_offset, blue_offset, and green2_offset registers. writes to these registers when manual_blc is set change the offsets being used. in automa tic blc mode, writes to these registers are effective when manual mode is re-entered. in manual_blc mode, no sampling or adjusting takes place for any color. digital black level calibration digital black level calibration is the final calc ulation applied to pixel data before it is output. it provides a precise black level to complement the coarser-grained analog black level calibration, and also corrects for black level shift introduced by digital gain. this correction applies to the active columns for all rows, including dark rows. test patterns the MT9P031 has the capability of injecting a number of test patterns into the top of the datapath to debug the digital logic. with one of the test patterns activated, any of the datapath functions can be enabled to exercise it in a deterministic fashion. test patterns are enabled when enable_test_pattern is set. only one of the test patterns can be enabled at a given point in time by setting the test_pattern_mode register according to table 16. when test patterns are enabled the ac tive area will receive the value specified by the selected test pattern and the dark pixels will receive the value in test_pattern_green for green pixels, te st_pattern_blue for blue pixels, and test_pattern_red for red pixels?+. note: aptina recommends turning off black level calibration (blc) when test pattern is enabled, otherswise some of the test patterns will not be properly output. table 16: test pattern modes test_pattern_mode test pattern output 0 color field (normal operation) 1 horizontal gradient 2 vertical gradient 3 diagonal gradient 4 classic test pattern 5walking 1s 6 monochrome horizontal bars 7 monochrome vertical bars
pdf: 09005aef81a4a477/source: 09005aef81a4a495 MT9P031_ds - rev. f 5/11 en 38 ?2005 aptina imaging corporation. all rights reserved. MT9P031: 1/2.5-inch 5mp digital image sensor features classic test pattern when selected, a value from test_data will be sent through the digital pipeline instead of sampled data from the sensor. the value will alternate between test_data for even and odd columns. color field when selected, the value for each pixel is determined by its color. green pixels will receive the value in test_pattern_green, red pixels will receive the value in test_pattern_red, and blue pixels will receive the value in test_pattern_blue. vertical color bars when selected, a typical color bar pattern will be sent through the digital pipeline. horizontal gradient when selected, a horizontal gradient will be produced based on a counter which incre- ments on every active pixel. vertical gradient when selected, a vertical gradient will be produced based on a counter which incre- ments on every active row. diagonal gradient when selected, a diagonal gradient will be produced based on the counter used by the horizontal and vertical gradients. walking 1s when selected, a walking 1s pattern will be sent through the digital pipeline. the first value in each row is 1. monochrome vertical bars when selected, vertical monochrome bars will be sent through the digital pipeline. the width of each bar can be set in test_pattern_bar_width and the intensity of each bar is set by test_pattern_green for even ba rs and test_pattern_blue for odd bars. monochrome horizontal bars when selected, horizontal monochrome bars will be sent through the digital pipeline. the width of each bar can be set in test_pattern_bar_width and the intensity of each bar is set by test_pattern_green for even bars and test_pattern_blue for odd bars. 8 vertical color bars table 16: test pattern modes (continued) test_pattern_mode test pattern output
pdf: 09005aef81a4a477/source: 09005aef81a4a495 MT9P031_ds - rev. f 5/11 en 39 ?2005 aptina imaging corporation. all rights reserved. MT9P031: 1/2.5-inch 5mp digital image sensor spectral characteristics spectral characteristics figure 26: typical spectral characteristics figure 27: cra vs. image height (7 deg) cra vs. image height plot image height cra (deg) (%) (mm) 000 5 0.178 0.35 10 0.356 0.70 15 0.535 1.05 20 0.713 1.40 25 0.891 1.75 30 1.069 2.10 35 1.247 2.45 40 1.426 2.80 45 1.604 3.15 50 1.782 3.50 55 1.960 3.85 60 2.138 4.20 65 2.317 4.55 70 2.495 4.90 75 2.673 5.25 80 2.851 5.60 85 3.029 5.95 90 3.208 6.30 95 3.386 6.65 100 3.564 7.00 cra design 0 2 4 6 8 10 12 14 0 10 20 30 40 50 60 70 80 90 100 110 image height (%) cra (deg)
pdf: 09005aef81a4a477/source: 09005aef81a4a495 MT9P031_ds - rev. f 5/11 en 40 ?2005 aptina imaging corporation. all rights reserved. MT9P031: 1/2.5-inch 5mp digital image sensor electrical specifications electrical specifications two-wire serial register interface the electrical characteristics of the two- wire serial register interface (sclk, s data ) are shown in figure 28 and table 17 on page 40. figure 28: two-wire serial bus timing parameters note: read sequence: for an 8-bit read, read waveforms start after write command and register address are issued. table 17: two-wire serial bus characteristics symbol definition condition min typ max unit f sclk serial interface input clock frequency C C C 400 khz t sclk serial input clock period C C C 2.5 sec sclk duty cycle C 40 50 60 % tr_sclk sclk rise time C 34 C ns tf_sclk sclk fall time C 8 C ns tr_sdat s data rise time C 34 C ns tf_sdat s data fall time C 10 C ns t srth start hold time write/read 0 10 28 ns t sdh s data hold write 0 0 0 ns t sds s data setup write 0 19.9 59.9 ns t shaw s data hold to ack write 279 281 300 ns t ahsw ack hold to s data write 279 281 300 ns t stps stop setup time write/read 0 0 0 ns t stph stop hold time write/read 0 0 0 ns t shar s data hold to ack read 279 284 300 ns t ahsr ack hold to s data read 279 284 300 ns t sdhr s data hold read 0 0 0 ns t sdsr s data setup read 0 19.9 59.9 ns c in _ si serial interface input pin capacitance C C 3.5 C pf c load _ sd s data max load capacitance C C 15 C pf r sd s data pull-up resistor C C 1.5 C k s data sclk write start ack stop s data sclk read start ack tr_clk tf_clk 90% 10% tr_sdat tf_sdat 90% 10% t sdh t sds t shaw t ahsw t stps t stph register address bit 7 write address bit 0 register value bit 0 register value bit 7 read address bit 0 register value bit 0 write address bit 7 read address bit 7 t shar t sdsr t sdhr t ahsr t srth t sclk
pdf: 09005aef81a4a477/source: 09005aef81a4a495 MT9P031_ds - rev. f 5/11 en 41 ?2005 aptina imaging corporation. all rights reserved. MT9P031: 1/2.5-inch 5mp digital image sensor electrical specifications i/o timing by default, the MT9P031 launches pixel data, fv and lv with the rising edge of pixclk. the expectation is that the user captures d out [11:0], fv and lv using the falling edge of pixclk. see figure 29 and table 18 for i/o timing (ac) characteristics. figure 29: i/o timing diagram table 18: i/o timing characteristics symbol definition condition min typ max unit f extclk1 input clock frequency pll enabled 6 C 27 mhz t extclk1 input clock period pll enabled 166 C 37 ns f extclk2 input clock frequency pll disabled 6 C 96 mhz t extclk2 input clock period pll disabled 125 C 10.4 ns t r input clock rise time 0.03 C 1 v/ns t f input clock fall time 0.03 C 1 v/ns t rp pixclk rise time 0.03 C 1 v/ns t fp pixclk fall time 0.03 C 1 v/ns clock duty cycle 40 50 60 % t (pix jitter) jitter on pixclk C C 1.03 ns t jitter1 input clock jitter 48 mhz C 300 C ps t jitter2 input clock jitter 96 mhz C 220 C ps t cp extclk to pixclk propagation delay nominal voltages 11.5 17.7 19.1 ns f pixclk pixclk frequency default 6 C 96 mhz t pd pixclk to data valid default 0.8 2.1 3.9 ns t pfh pixclk to fv high default 2.8 4.3 5.9 ns t plh pixclk to lv high default 2.2 3.5 5.9 ns t pfl pixclk to fv low default 2.4 4.2 5.9 ns t pll pixclk to lv low default 2.6 4.1 5.9 ns c load output load capacitance C <10 C pf c in input pin capacitance C 2.5 C pf data[7:0] frame_valid/ line_valid frame_valid leads line_valid by 609 pixclks. frame_valid trails line_valid by 16 pixclks. pixclk *pll disabled for t cp extclk t cp t r t extclk t f t rp t fp t pd t pd t pfh t plh t pfl t pll pxl _0 pxl _1 pxl _2 pxl _n 90% 10% 90% 10%
pdf: 09005aef81a4a477/source: 09005aef81a4a495 MT9P031_ds - rev. f 5/11 en 42 ?2005 aptina imaging corporation. all rights reserved. MT9P031: 1/2.5-inch 5mp digital image sensor electrical specifications dc electrical characteristics the dc electrical characteristics are shown in table 19, table 20 on page 43, and table 21 on page 43. table 19: dc electrical characteristics symbol definition condition min typ max unit v dd core digital voltage 1.7 1.8 1.9 v v dd _io i/o digital voltage 1.7 1.8/2.8 3.1 v v aa analog voltage 2.6 2.8 3.1 v v aa _pix pixel supply voltage 2.6 2.8 3.1 v v dd _pll pll supply voltage 2.6 2.8 3.1 v v ih input high voltage v dd _io = 2.8v 2 C 3.3 v v dd _io = 1.8v 1.3 C 2.3 v v il input low voltage v dd _io = 2.8v C0.3 C 0.8 v v dd _io = 1.8v C0.3 C 0.5 v i in input leakage current no pull-up resistor; v in = v dd _io or d gnd C<10C?a v oh output high voltage v dd _io = 1.8v 1.3 C 1.82 v v dd _io = 2.8v 2.3 C C v v ol output low voltage v dd _io = 2.8v 0.16 C 0.35 v v dd _io = 2.8v C C 0.6 v i oh output high current at specified v oh = v dd _io - 400mv at 1.7v v dd _io 8.9 C 22.3 ma i ol output low current at specified v ol = 400mv at 1.7v v dd _io 2.6 C 5.1 ma i oz tri-state output leakage current v in = v dd _io or gnd C C 2 a i dd 1 digital operating current parallel mode 96 mhz full frame nominal voltage, pll enabled C2835ma i dd _io1 i/o digital operating current parallel mode 96 mhz full frame nominal voltage, pll enabled C38.650ma i aa 1 analog operating current parallel mode 96 mhz full frame nominal voltage, pll enabled C7280ma i aa _pix1 pixel supply current parallel mode 96 mhz full frame nominal voltage, pll enabled C2.46ma i dd _pll1 pll supply current parallel mode 96 mhz full frame nominal voltage, pll enabled C56ma i dd 2 digital operating current parallel mode 96 mhz 4x binning nominal voltage, pll enabled C1535ma i dd _io2 i/o digital operating current parallel mode 96 mhz 4x binning nominal voltage, pll enabled C6.450ma i aa 2 analog operating current parallel mode 96 mhz 4x binning nominal voltage, pll enabled C6980ma i aa _pix2 pixel supply current parallel mode 96 mhz 4x binning nominal voltage, pll enabled C3.46ma i dd _pll2 pll supply current parallel mode 96 mhz 4x binning nominal voltage, pll enabled C56ma i stby 1 hard standby current pll enabled extclk enabled C <500 C a i stby 2 hard standby current pll disabled extclk disabled C <50 C a i stby 3 soft standby current pll enabled extclk enabled (pll enabled) C <500 C a i stby 4 soft standby current pll disabled extclk enabled (pll disabled) C <500 C a
pdf: 09005aef81a4a477/source: 09005aef81a4a495 MT9P031_ds - rev. f 5/11 en 43 ?2005 aptina imaging corporation. all rights reserved. MT9P031: 1/2.5-inch 5mp digital image sensor electrical specifications caution stresses greater than those listed in table 21 may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. note: 1. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. to keep dark current and shot noise artifacts from impacting image quality, care should be taken to keep t op at a minimum. table 20: power consumption mode full resolution (15 fps) 4x binning unit streaming 381 262 mw table 21: absolute maximum ratings symbol definition condition min max unit v dd _max core digital voltage C0.3 1.9 v v dd _io_max i/o digital voltage C0.3 3.1 v v aa _max analog voltage C0.3 3.1 v v aa _pix_max pixel supply voltage C0.3 3.1 v v dd _pll_max pll supply voltage C0.3 3.1 v v in _max input voltage C0.3 3.4 v i dd _max digital operating current C 35 ma i dd _io_max i/o digital operating current C 100 ma i aa _max analog operating current C 95 ma i aa _pix_max pixel supply current C 6 ma i dd _pll_max pll supply current C 6 ma t op operating temperature measure at junction C30 70 c t st storage temperature C40 125 c
pdf: 09005aef81a4a477/source: 09005aef81a4a495 MT9P031_ds - rev. f 5/11 en 44 ?2005 aptina imaging corporation. all rights reserved. MT9P031: 1/2.5-inch 5mp digital image sensor package dimensions package dimensions figure 30: 48-pin ilcc package outline drawing note: 1. all dimensions in millimeters. 4.50 10.000 0.075 3.85 7.70 3.85 0.70 typ 0.70 typ 7.70 48 1 1.40 47x 0.80 48x 0.40 4.50 10.000 0.075 7.57 1.455 5.702 ctr 7.02 4.277 ctr 1.45 c l c l lead finish: gold plating, 0.50 microns minimum thickness 4.20 5.000 0.075 optical center c b optical area maximum rotation of optical area relative to package edges b and c : 1o maximum tilt of optical area relative to seating plane a : 25 microns relative to top of cover glass d : 50 microns 5.000 0.075 optical center first clear pixel seating plane mold compound: epoxy novolac image sensor die lid material: borosilicate glass 0.40 thickness 1.250 0.125 0.725 0.075 0.525 0.050 0.125 (for reference only) substrate material: plastic laminate a d
pdf: 09005aef81a4a477/source: 09005aef81a4a495 MT9P031_ds - rev. f 5/11 en 45 ?2005 aptina imaging corporation. all rights reserved. MT9P031: 1/2.5-inch 5mp digital image sensor appendix aC power-on and standby timing appendix aC power-on and standby timing figure 31: power-on and standby timing diagram note: 1. aptina recommends 1ms. 2. v aa must stabilize before reset_bar goes high. 3. aptina recommends that the chip is paused (restart_pause register) prior to standby_bar = 0 or restarted (restart register) on resumption of operation. extclk two-wire serial i/f sclk, sdata reset_bar v dd , v dd_ io v aa , v aa_ pix, v dd_ pll data output standby_bar min 10 sysclk cycles standby standby wake up active driven = 0 low-power non-low-power responds only to chip_enable and invert standby registers when standby_bar = 0 d out [9:0] power up non-low-power min 10 sysclk cycles active power down d out [9:0] note 3 min 10 sysclk cycles d out [9:0] high-z note 3 min 1ms note 2 note 1 note 1
10 eunos road 8 13-40, singapore post center, singapore 408600 prodmktg@aptina.com www.aptina.com aptina, aptina imaging, and the aptina logo are the property of aptina imaging corporation all other trademarks are the property of their respective owners. this data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. alt hough considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. MT9P031: 1/2.5-inch 5mp digital image sensor revision history pdf: 09005aef81a4a477/source: 09005aef81a4a495 . MT9P031_ds - rev. f 5/11 en 46 ?2005 aptina imaging corporation all rights reserved. revision history rev. f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/3/11 ? updated table 19, ?dc electric al characteristics,? on page 42 ? removed es from table 1, ?available part numbers,? on page 1 ? removed registers and created separate register reference ? updated ?standby and chip enable? on page 23 ? replaced figure 26: ?typical spectral char acteristics,? on page 39 with latest curve rev. e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7/10 ? updated to non-confidential rev. d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/10 ? updated to aptina template ? updatedtable 13: register description on page 25 with new column width equation rev. c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9/07 ?update table18: i/o timing characteristics on page 41 rev. b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .08/07 ?update v dd q to v dd _io ? update reset# to reset_bar ? update standby# to standby_bar ? update oe# to oe ? update table 18, ?i/o timing characteristics,? on page 41 ? update table 19, ?dc electrical characteristics,? on page 42 ? update table 21, ?absolute maximum ratings,? on page 43 ? add "appendix a? power-on and standby timing" on page 45 ? add figure 31: ?power-on and standby timing diagram,? on page 45 rev. a, production. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .06/06 ?initial release

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